Structured Digital Design and Simulation 1

TITLE Structured Digital Design and Simulation 1
MODULE CODE SDDS H6000
CREDITS 10
NFQ LEVEL 9
MODULE DESCRIPTION To enable the student to analyse new problems and formulate structured design solutions using digital circuits which require a multi-input multi output system controller. To assess and take account of real-world architecture restrictions of some available technologies in the design solution, and to code solution in Verilog and test the solution
   
LEARNING OUTCOMES  
1 To design synchronous state machines to solve real world engineering problems
2 To evaluate a complex problem and architect a solution to partition a digital design problem into logical subsections and to design solutions to these subsections that integrates well with the overall solution
3 To write Verilog/SystemVerilog Code to efficiently and clearly represent a digital system comprising FSMs, design blocks and functional partitions
4 To design and code a verilog based testbench to unit test a design block
5 To evaluate a range of memory technologies and select appropriate technology for a given design problem and compare and contrast to other possible solutions
6 To design solutions to designs involving a range of AMBA bus protocols
7 To evaluate and apply design methods to solve problems involving asynchronous signals and asynchronous interfaces
8 To be able to propose, design and document technical solutions adhering to prescribed guidelines.
   
INDICATIVE CONTENT  
Synchronous Finite State Machine Design and Analysis Synchronous Finite State Machine Design and Analysis: Word problem to FSM design and Documentation. Implementation of FSMs using Flip Flops and logic gates. Derivation of timing diagrams from logic design. Timing Diagram specification to FSM design and documentation. Applying FSM techniques to real world problems.
Introduction to Verilog/ System Verilog Introduction to Verilog. Datatypes for Logic, Registers, wires. Coding of a schematic. Coding FSMs. Coding of testbenches
Digital System Partition Digital System Partition – How and When Context Diagrams, Dataflow diagrams, Functional Partitions and their use in breaking down complex problems into designable sub-systems. Clock period constraints and its effect on system architecture including pipelining and
  Dataflow. Applied system partition techniques to real world problems Power Analysis.
Digital system Realisation Clocking methods and Clocking limitations. Logic depth estimation. Cost comparisons of different alternatives. Single bit Asynchronous Inputs to FSMs and synchronization methods. Metastability and Reliability of single bit and double synchronisation methods. Design Method to safely facilitate bus crossing asynchronous interface. Using FIFOs to Interface between asynchronous digital sub-systems
Design Lifecycle FPGAs - Overview of the architecture and building blocks of XILINX, Altera(Intel) and Microsemi FPGAs. Comparison of FPGA to ASIC development. IO Standards, DDR Memory and DDR interfacing. ARM and AMBA, APB, AHBLite and AXI4 buses, how they work and compare. Design of AMBA bus DMA controller using one of the AMBA protocols.
Quality and Reliability Quality and Reliability in Electronic Systems. MTBF and the factors involved. Quality of Design, Design Bugs and their elimination – design reviews. Implementation bugs – crosstalk, reflections, simultaneous switching and solution approaches. Failure in systems design and case studies. Ethics in Design Engineering